As a programmable logic circuit of the related art, there is a one disclosed in Japanese patent document 1. This programmable logic circuitry of the related art consists of dynamically reconfigurable field-programmable logic devices employing dynamically connected arrays, latch circuits, and dynamic logic cores that are gradually being executed in circuits. With programmable logic circuits of the related art, in the case of implementing large scale logic circuits, a plurality of the programmable logic circuits are connected in series, and logic processing of each level is executed sequentially.
In this case, with programmable logic circuits of the related art, control is performed such that when an internal level of a first chip reaches a specified level, a next chip is operated using a circuit level counter indicating the circuit level and an internal counter indicating the internal level. Namely, programmable logic circuits of the related art are implemented in such a manner that circuit level is divided in chip units. Patent Document 1: Japanese Patent Application Laid-Open No. Hei 8-510885.